LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all; 

entity file_out is
--  port( data_out : in std_logic_vector(499 downto 0) 
--  );
end file_out;

architecture send_output of file_out is
-- signal clock,eof : bit := '0';     --period of clock,bit for indicating end of file.
   
  signal data_out : std_logic_vector(499 downto 0);        --data to be saved into the output file.
 
  begin
  
  -- clock <= not (clock) after 1 ns;     --clock with time period 2 ns
  data_out <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111000000001100000000000000000000000000000000000000000000000000000000000000000000000000";
  
  writing :
  process
    file out_file : text open write_mode is "/home/ecegrid/a/mg114/ece337/puece337-hdacontroller/test_io/tb_output.txt";       --declare output file
    variable out_line : line;                                      --declare line number 
    variable data_to_save : bit_vector(499 downto 0);        --data to be saved into the output file.
    
  begin
  --  wait until clock = '0' and clock'event;    
  wait for 1 ns;
  data_to_save := to_bitvector(data_out);                         --puts the value available in signal into a variable
  wait for 1 ns;
    
    for I in 499 downto 0 loop                    --go through every bit in the signal
      
      write(out_line, data_to_save(I), RIGHT, 1);    --write bit to a line(linenumber,value,justified,field);
      writeline(out_file, out_line);              --write line to external file.
    end loop;
    
    wait;
  end process writing;
  
end send_output;
